1. Field of the Invention
This present invention relates to a semiconductor memory device and a manufacturing method thereof, for example, a nonvolatile semiconductor memory device and its manufacturing method that are suitable for high integrality.
2. Description of the Related Art
A top view of a conventional NOR type non volatile semiconductor memory device is shown in FIG. 8. As shown in FIG. 8, a plurality of element region (ER) are arranged in a horizontal direction of the FIG. 8. Each of the element regions is electrically separated from each other by element isolation regions STI (Shallow Trench Isolation). A plurality of word lines WL1 portions of which are used as gate electrodes are arranged in a vertical direction of FIG. 8 so as to intersect each of the element regions.
Drain contacts 102a are arranged between two word lines WL1 and connects between a drain region formed on a upper surface of the semiconductor substrate 100 and a bit line 115. The drain contact 102a is used in common at memory cells that are arranged at both sides of the drain contact 102a. 
A source line 103 is arranged in parallel to the word line WL1 at an opposite side where the drain contacts 102a are not formed. The source line 103 is connected to source regions that are formed on an upper surface of the semiconductor substrate 100. A source contact 102b is formed on the source line 103. The source contact 102b is connected between the source line 103 and another line (not shown) that is formed in a same layer as the bit line 115.
FIGS. 6 and 7 show cross sectional views of the A—A and the B—B shown in FIG. 8 respectively. As shown in FIG. 8, a plurality of element isolation regions (STI) are formed on an upper surface of the semiconductor substrate 100, thereby forming a plurality of element regions each of which is arranged between the two element isolation regions. A word line WL1 is formed so as to intersect each of the element regions.
As shown in FIGS. 6 and 8, the word line WL1 is formed on a silicon oxide layer 101 (a first gate insulating film) that is formed on the semiconductor substrate 100. The word line WL1 also includes a poly crystalline silicon layer 104 that is used as a first floating gate, a poly crystalline silicon layer 105 that is used as a second floating gate, an ONO layer 106 that is used as a second gate insulating film, a control gate electrode comprised of a poly crystalline silicon layer 107 and a tungsten silicide layer 108 (WSi), and a TEOS layer 109 that was used as a mask layer to form a gate electrode.
A silicon nitride layer 110 is formed on the side surface of the word line WL1. A silicon nitride layer 111 is formed to cover the silicon nitride layer 110. Silicon oxide layers 112 and 131 are formed to fulfill between gate electrodes covered by the silicon nitride layer 111. And then, portions of the silicon oxide layers 112 and 131 are removed and flatted by using a CMP method.
Conventionally, drain contacts 102a and source line 103 are formed at different manufacturing steps. First, the source line 103 is formed, and then the drain contacts 102a are formed. Details of the manufacturing step are as follows.
Portions of a silicon oxide layer 101, a silicon nitride layer 111, silicon oxide layers 112 and 131 are removed to a direction vertical to the element region and the element isolation region, and parallel to the word line WL1 by using a RIE method (Reactive Ion Etching), thereby forming a contact hole to reach source regions that are formed on an upper surface of the semiconductor substrate 100. And then, a metal layer 114b, for instance, tungsten layer W is formed in the contact hole, thereby forming a source line 103.
After that, a silicon oxide layer 113 that is used as an interlayer insulating layer is formed and flatted by using a CMP (Chemical Mechanical Polishing) method. At positions where the source line 103 is not formed, portions of a silicon oxide layer 101, a silicon nitride layer 111, silicon oxide layers 112, 131, and 113 are removed so as to expose upper surfaces of the silicon substrate 100 by using a RIE method, thereby forming contact holes. A metal layer 114a, for instance, tungsten W is then formed in the contact hole, thereby forming drain contacts 102a. After that, a portion of the silicon oxide layer 112 is removed so as to expose an upper surface of the source line 103 by using a RIE method, thereby forming a contact hole. A metal layer 116, for instance, tungsten W is then formed in the contact hole, thereby forming a source contact 102b that electrically connects between the source line 103 and line layer (not shown).
It is noted that conventional semiconductor memory devices with source line structures are shown in following materials. IEDM98-975-978 (Novel 0.44 μm2 Ti-Salicide STI Cell Technology for High-Density NOR Flash Memories and High Performance Embedded Application), Japanese patent laid open Hei10-326896, Hei6-334156, Hei7-74325, Hei11-265947, 2002-76147, Hei9-129854, and 2001-68571.
The conventional semiconductor memory device has a following problem. In the conventional semiconductor memory device, the drain contact 102a is formed after the source line 103 and the silicon oxide layer 113 are formed. Therefore, it is necessary to form a contact hole with a depth that is total thickness of the source line 103 and the silicon oxide layer 113, and fulfill the metal layer 114a in the contact hole. In this result, an aspect ratio of the contact hole is higher and it is difficult to fulfill the metal layer 114a in the contact hole, thereby resulting in occurrence of voids and a poor conduction.
It is necessary to use different photo resist masks when a RIE method is achieved in order to form the source line 103 and the drain contact 102a. Furthermore, it is necessary to form a contact hole of the source contact 102b so as to connect between the source line 103 and a conductive line. In this result, the source contact 102b may be deviated from the source line 103, thereby resulting in a poor conduction.